Increases in the integration levels of integrated circuit memory devices may result in concomitant increases in the power consumption requirements of memory devices. Accordingly, attempts have been made to improve the power consumption efficiency of circuits that make up an integrated circuit memory device. Unfortunately, such attempts to improve power consumption efficiency may cause a reduction in the reliability of highly integrated memory devices.
FIG. 1 is a block diagram of a conventional integrated circuit memory device (e.g., DRAM device). As illustrated, the memory device includes control logic 80, an internal power supply voltage generator 90, a row address buffer 10, a column address buffer 20, a row decoder 30, a memory cell array 50, a sense amplifier 60, a column decoder 40, a data input buffer 70a and a data output buffer 70b. As illustrated by FIGS. 1-2, the internal power supply voltage generator 90 generates an internal supply voltage signal AIVC in response to an external supply voltage signal EVC. In particular, the internal power supply voltage generator 90 operates to actively pull up signal line AIVC when signal line PAIVCE is set to a logic 1 level, however, when signal line PAIVCE is set to a logic 0 level, the internal power supply voltage generator 90 does not supply pull-up current to signal line AIVC. The logic 1 pulse width of signal PAIVCE is typically directly related to the active pulse width of the row address strobe signal /RAS. As illustrated by FIG. 2, increases in the external supply voltage EVC above a predetermined clamping level (e.g., 2.5 volts) will not result in further corresponding increases in the magnitude of the signal provided to signal line AIVC.
Referring now to FIG. 3, an operation to read data from a memory cell within the array 50 includes the step of driving a corresponding word line WL to an active level (i.e., logic 1 level). In response, charge from within the memory cell will be transferred to a corresponding bit line BL and the bit line will rise slightly in potential. If the sense amplifier 60 is active (LANG=1, LAPG=0), the sense amplifier will use current provided by signal line AIVC to amplify and drive the differential bit lines BL and /BL to opposite logic levels, as illustrated. During this amplification operation, the voltage level on signal line AIVC may drop. Moreover, because the internal power supply voltage generator 90 may only operate to actively pull-up signal line AIVC while signal line PAIVCE is at a logic 1 level, the signal line AIVC may not return to a voltage level of 2.5 volts at the time the signal line PAIVCE transitions from 1-0. The reduction is illustrated by the amount ".DELTA.V". If this happens, the differential bit lines may not be driven to their full rail-to-rail levels and the reliability of data restore operations (when charge is transferred back into the selected memory cells to restore the data therein) may be reduced. This likelihood of reduced reliability may also be increased if the duration of the active row address strobe signal /RAS is decreased to achieve higher frequency of operation. Thus, notwithstanding attempts to develop more highly integrated memory devices, there continues to be a need for memory devices that can be more reliable when operating at relatively low voltage levels and at high frequencies.